DC voltage converters and regulators are well-known in the art and are widely employed to ensure that the DC voltage provided to electronic devices is of the correct value independent of variations in the available supply voltage or the load presented by the device being powered. For example, most battery-operated consumer electronics devices use DC-DC regulators to convert the 2.7-5.5 V battery voltage down to a 0.56-3.4 V operating voltage required by the on-board integrated circuits. Voltage regulators are universally used to convert the battery voltage to the desired fixed value to be supplied to the integrated circuit, and to ensure that value remains constant as the battery ages and the current used by the integrated circuit changes.
Voltage regulators can be classified as either linear mode or switched mode. A linear regulator is essentially a resistive load placed in series (or in parallel) with the load to be powered; the resistance of the regulator is adjusted by a control circuit to ensure that the voltage at the regulator output is constant. In contrast, a switched regulator converts a DC input voltage to a time-varying voltage or current, and then makes use of rectifying or switching elements and passive components such as inductors and capacitors, in conjunction with a control circuit, to re-convert this time-varying signal to a DC voltage at a fixed value differing from the input voltage. FIG. 1 shows an example of a prior art linear voltage regulator and a prior art switching mode voltage regulator.
Linear regulators are simple to implement, fast-acting, and compact. Further, they do not radiate interfering signals (EMI). However, they have two important limitations. First, a linear regulator can only reduce and not increase the voltage presented to it. Secondly, linear regulators are very inefficient in many applications (or in cases where the output voltage is not slightly below the input voltage). Efficiency is defined as the ratio of output power divided by input power. In the case of an ideal linear regulator (in which no power is dissipated in the control or regulatory circuitry), the efficiency can be no better then Vout/Vin, where Vout is the output voltage of the regulator and Vin is the input voltage of the regulator. Thus, when a substantial reduction in the input voltage is called for by the application, a linear regulator must inevitably provide poor efficiency. Other regulator topologies, such as a shunt linear regulator, (wherein the regulator acts as a variable resistor in parallel with the load), can also be used, but produce substantially similar results. Particularly in the case of battery-powered devices, inefficient voltage regulation directly impacts the expected battery life and thus is highly undesirable. As a consequence of these limitations, switched mode converters are used for many electronic applications, particularly those where energy efficiency and/or battery life are of critical importance.
Unfortunately, most switched mode regulators require large valued (and physically large and thick) external inductors and capacitors to operate. To understand why, let us consider as an example a typical prior-art voltage-reducing (“buck”) converter, shown in simplified form in FIG. 2 (note that the transistors might be PMOS or NMOS devices). The resulting time-dependent inductor current in the limit of ideal (instantaneous) switching is shown in FIG. 3. In operation, the series switching transistor Qseries is switched on for a time interval Ton, allowing current to flow from the supply through the output inductor Lout. During this time period Ton, the output current 101 grows linearly with time, at a rate proportional to the difference between the input and output voltages, the latter being substantially fixed during the switching cycle if a sufficiently large output capacitor value Cout is employed:
                                          ⅆ                          I              out                                            ⅆ            t                          =                  (                                    (                                                V                                                                                                    ⁢                                          i                      ⁢                                                                                          ⁢                      n                                                                      -                                  V                  out                                            )                                      L              out                                )                                    (        1        )            At the expiration of Ton, the switch Qseries is turned off. After a short dead time, the switch Qshunt, is then turned on, and the inductor current flows from ground through Qshunt. Again the current 102 changes linearly with time, in this case decreasing with increasing time:
                                          ⅆ                          I              out                                            ⅆ            t                          =                              -                          V              out                                            L            out                                              (        2        )            
The current through the output inductor thus varies with time; this variation is known as inductor current ripple. For any given inductor value, if the time Toff during which the series switch Qseries is off is long enough, the inductor current will decrease to zero value and either reverse direction or be terminated by turning Qshunt off. The mode of operation in which current is terminated is known as “discontinuous” operation, in order to distinguish it from “continuous” operation, in which current is always being delivered to the load from the output inductor. In most practical converter designs, the variation in current with time (the ripple current) is chosen to be less than about 20 percent of the average output current, as a rule-of-thumb. The requirement for limiting ripple to 20% of the average current sets a minimum inductance value requirement:
                              L                      m            ⁢                                                  ⁢            i            ⁢                                                  ⁢            n                          =                                            V              out                                      0.2              ⁢                              (                                  I                  out                                )                                              ⁢                                    1              -                                                V                  out                                /                                  V                                      i                    ⁢                                                                                  ⁢                    n                                                                                      f              s                                                          (        3        )            where (Iout) is the average output current of the converter and fs is the switching frequency. This relationship is depicted graphically in FIG. 4 for typical values of parameters relevant to mobile devices. (The line shown in the figure is specific to the 20% ripple limit mentioned above, and would shift position slightly if a different criterion were applied.) For converters operating in the traditional switching frequency range of 50 kHz to 1 MHz, it is apparent that inductors of on the order of 3 to 30 μH are required for continuous operation.
Such large inductance values are normally achieved by wrapping a conductor around a ferromagnetic core, greatly increasing the inductance obtained for a given number of turns of a given radius. At sufficiently low frequencies, these inductors have very low losses. However, they have several disadvantages.
The materials used to magnetically enhance the inductor have limitations on operational temperature (typically to −30 to +85° C.), and limitations on the peak current due to core saturation effects. A ferromagnetic material reaches saturation when the magnetization in the core material no longer increases in response to an increase in the magnetizing field from the windings. Saturation occurs when the magnitude of the magnetizing field is larger than a maximum value; the maximum value falls with increasing temperature, and is greatly reduced at high frequencies (typically >20 MHz). Core saturation leads to a significant reduction in inductance and an increase in loss, (both of the latter due to a large increase in inductor current). Therefore, the inductor cannot be allowed to saturate during normal regulator operation.
As a result, a magnetically-enhanced inductor must be carefully designed and selected for the application. For example, for the buck converter depicted in FIG. 2, the maximum load current is:
                                          I                          load              ,                              ma                ⁢                                                                  ⁢                x                                              =                                    I                              out                ,                                  ma                  ⁢                                                                          ⁢                  x                                ,                                  D                  ⁢                                                                          ⁢                  C                                                      -                          I                              out                ,                                  p                  -                  p                                                                    ⁢                                  ⁢                              I                          out              ,                              p                -                p                                              =                                                    I                                  m                  ⁢                                                                          ⁢                  ax                                            -                              I                                  m                  ⁢                                                                          ⁢                  i                  ⁢                                                                          ⁢                  n                                                      =                                          (                                                      V                                          i                      ⁢                                                                                          ⁢                      n                                                        -                                      V                    out                                                  )                            ⁢                                                V                  out                                                  V                                      i                    ⁢                                                                                  ⁢                    n                                                              ⁢                              1                                                      f                    s                                    ⁢                                      L                    out                                                                                                          (        4        )            Here Iout,max,DC is the largest current that can flow in the output inductor without experiencing saturation. Iout,p-p is the peak-to-peak variation in current as depicted in FIG. 3, and is expressed in terms of the input and output voltages and switching frequency under the assumption of ideal switching used previously.
For a given application, the maximum load current and the input and output voltages are fixed requirements. Thus, the core must be sized to support the required current for the application. Switching frequency can be increased to reduce the peak current encountered, but as noted above, at high frequencies the saturation magnetization falls, setting a limit on how much improvement can be obtained in that manner. At higher frequency the core losses begin to increase rapidly and efficiency falls.
Most importantly, magnetic inductors are most typically fabricated by winding wire around a magnetic core. Wound magnetic inductors are bulky compared to components integrated on a semiconductor chip. Market demands for consumer electronics are driving component suppliers to create the thinnest and smallest devices possible. For battery-operated devices, the height of the electronic components mounted in the internal printed circuit board (PCB) is usually limited by the thickness of the inductors used for DC-DC power conversion. In addition, as discussed above, wound magnetic inductors are best suited for operation at frequencies of a few MHz or below. The capacitor Cout of FIG. 2 acts with the output inductor Lout to filter the output voltage. In order to ensure minimal output ripple, the capacitance must have a large enough value to store the time-varying charge delivered during the switching cycle without significant variation in the voltage across the capacitor. For converters operating at 10 MHz or less, the capacitor is typically 5 μF or larger, again adding substantially to the size and expense of the converter. Additionally, a capacitor is needed at the input of the converter, which is somewhat larger, or somewhat smaller in value compared with the output capacitor. For example, 0.5 times to 2 times the value of the output capacitor.
From equation (3) and FIG. 4, it is apparent that the size of the inductor can be reduced if the switching frequency is increased. Values of a few tens of nH can be considered for switching frequencies in the tens to hundreds of MHz. As an ancillary benefit, the required filter capacitor values are also reduced. The use of lower-valued inductors allows use of planar geometries that can be integrated on printed-circuit boards or fabricated in integrated circuits. While magnetic materials may still be employed, their deposition requires additional process steps and thus adds cost. At increasing switching frequency, most magnetic materials have reduced permeability and increased tosses, though the exact behavior varies widely depending on the material and fabrication techniques employed. Therefore it is of interest to combine high-frequency switching with non-magnetically-enhanced inductors to realize compact, efficient switched mode DC-DC converters.
Increasing the switching frequency to 10 to 100 MHz or higher, while maintaining high efficiency, requires that losses within the switches be minimized. Switching losses arise from two independent sources, depicted in a simplified fashion in FIG. 5. The switch voltage and current are depicted qualitatively versus time in 110. During the time when a switch is open (in the case of a transistor, the applied gate voltage is such as to eliminate the conductive channel), it sustains a substantial voltage but very little current flows through it, so tosses are negligible. Similarly, when the switch is closed (when the gate voltage is set so as to enhance channel conductivity), large currents flow but relatively little voltage appears across the switch (due to the supposedly low transistor on-resistance RON), so losses are again low. However, during the time Tsw when the transistor transitions from the open to closed state, or vice versa, large voltages and currents may be simultaneously present, and losses can be substantial due to power being dissipated across the switching devices. These losses are on the order of the product of operating current, voltage, and switching time, and occur twice each cycle. For a buck converter with symmetrical switching of the series and shunt transistors, and a simple linear dependence of the current and voltage on time, we have:
                              P          switch                ≈                              2            3                    ⁢                      I            out                    ⁢                      V            max                    ⁢                      T            sw                    ⁢                      f            s                                              (        5        )            where Pswitch is the power dissipated by the two switching transistors when switching at frequency fs, Tsw is the time required for the transistor to switch on or off, and Vmax is the voltage present on the switch in the open state immediately prior to closing, or just after opening. For a fixed switching time Tsw, these losses increase with switching frequency fs.
Secondly, the voltage on the gate of a transistor must be changed in order to switch its state from open to closed or closed to open. In order to change the voltage, a quantity of charge proportional to the capacitance Cgate of the transistor must be added to or removed from the gate by the driver circuitry 130. Charging the gate capacitance to a voltage Vgate through a resistive series element requires an energy 120 of Cgate Vgate2, which must be supplied for each switching cycle; this energy is lost when the charge ultimately finds its way to ground (unless some sort of charge recycling is used), resulting in a minimum dissipation proportional to frequency for each switching transistor:Pgate=Cgate=Vgate2fsw  (6)
Prior art solutions to the problem of dissipation within the transistor channel during switching at high frequencies have been directed towards minimizing the drain-source voltage Vmax. In the limit where the voltage across each transistor is 0 at the time when the state of the transistor is changed, little or no power is dissipated during the switching event. This condition is known as soft-switching or zero-voltage switching (ZVS). (Analogous approaches exist for switching at zero current through the switching device, known as Zero Current Switching, and offering benefits and challenges.) An example of the control timing used in this approach is shown in FIG. 6, with a typical prior art circuit shown in FIG. 7. Zero-voltage switching depends on the use of a non-overlap or dead time during which both the series and shunt switches are off, such as time intervals 206 and 207. During this time, current into or out of the node Vsw continues to flow due to the large inductor Lout, causing the node voltage 208 to change. When the series switch control voltage 201 goes high to turn the series switch Qseries off, the node voltage 208 falls; if the shunt switch control voltage 202 goes high just as the voltage 208 crosses 0, little or no voltage is present between the transistor drain and source at the moment of switching, and switching loss is reduced. However, in dead time 207, when the shunt switch is turned off under normal low-ripple operation, the node voltage again increasing the voltage presented to the series switch. In order to achieve ZVS on both switching elements, it is necessary that the inductor ripple current exceed the average current, so that current flows into the Vsw node during the portion of the switching cycle 205, when the shunt switch control 202 has gone low but the series switch control 201 is still high. The node voltage 208 will then rise as current flows into the node; when the node voltage equals that supplied to the series switch, the series switch control voltage 201 goes low, so that turn-on of the series transistor Qseries also occurs at near zero voltage across the transistor, minimizing loss therein. The rate at which the voltage Vsw varies during the time both switches are off is determined by the ratio of the node current and capacitance. The node capacitance may intrinsically be very small, causing rapid changes in voltage and making it difficult to maintain correct switch timing, so it is typical to add capacitance to the node or in parallel with the switching transistors, depicted in FIG. 7 as Cseries and Cshunt, to simplify the problem of accurate switch timing.
To minimize dissipation due to switching of the capacitive load presented by the switching transistors, prior art work has focused on designs that store the gate capacitor switching energy in additional inductive elements, forming a resonant converter (FIG. 8). As is well-known, series resonant circuits can maintain large voltages across the individual elements with very low toss if the ratio of reactance to resistance of each element is large. However, such circuitry operates optimally only over a narrow band of frequencies and presents substantially sinusoidal voltages to the constituent components, so pulse-width modulation (PWM) cannot generally be used to control the output voltage, and other means such as frequency variation or on-off control must be substituted. Finally, the use of a resonant input may lead to large voltage swings on the switching transistor gates in order to ensure fast switching transients, which can cause reliability problems.
An alternative approach to minimizing both sources of switching loss is to employ very fast switching times, thus reducing the term Tsw in equation (5). The time required to switch the transistor should be a small fraction of the switching control period. For operation at 100 MHz, where the switching control period is 10 nsec, the time Tsw for a sinusoidal voltage (appropriate for use in a ZVS converter) is about 1.6 nsec. In order to achieve comparable switching dissipation when switching at a finite voltage, the switching time Tsw should be no more than about ⅕ of this time, or 350 psec.
Advanced transistors using very short channel lengths and very thin oxides, with reduced area consumption and lower turn-on voltages, are necessary to implement such fast switching times. By using such technologies, capacitance is minimized (for the same RON) and the voltage required to change the transistor state is reduced, and thus gate switching loss is also reduced. Table 1 summarizes typical values of some key figures of merit for CMOS technologies as a function of technology generation (expressed as the minimum feature size Lmin). It is clear that for more advanced technology generations, the energy needed to charge a unit gate area to the maximum allowed voltage falls precipitously, reducing the gate switching loss. (The simple figure of merit shown here underestimates the resulting benefit, because the area required to achieve a given on resistance also falls for smaller feature sizes.) The minimum delay also falls, and thus the product of the time needed to change the state of a switch and the switching frequency, which determines the channel switching loss, falls from a substantial value of 12% for 0.5 micron transistors, to a negligibly small value of 1.5% for 65 nm structures.
TABLE 1Key converter parameters for different generationsof silicon CMOS fabrication technology.VmaxMinimumGate2TswLminCgateKnDCVtdelayenergy*fsw0.5360519437.57.5%0.355803.3110027.2 8%0.2561002.70.85921.94.7%0.1881301.80.655213.04.2%0.1391501.30.55417.63.2%0.09101601.10.45236.11.9%0.065101601.10.4116.10.9%
TABLE 2Explanation of the parameter names used in Table 1.ParameterDescriptionUnitsLminMinimum dimension characteristic of a given micronstechnology generation.CgateGate capacitance of the standard MOS transistor.fF/μm2KnTransconductance parameter of NMOS device.μA/V2Vmax DCMaximum allowed value of Vgs or Vds, measured Vat DCVtThreshold voltage of MOS transistor.VDelayCharacteristic delay for matched inverters (ring  oscillator), estimated as               T      switch        ≈                  2        ⁢                                  ⁢        β        ⁢                                  ⁢                  L          min          2                                      μ          n                ⁡                  (                                    V                              max                ⁢                                                                  ⁢                DC                                      -                          V                              t                ⁢                                                                                                )                      ⁢           where μn is the electron mobility estimated from the measured gate capacitance and transconductance parameter, and □ is an empirical constant adjusted to agree with simulation results at Lmin = 0.18 micron.PsGate Energy to charge 1 square micron gate to VmaxfJenergy2Tsw*fswRelative percentage of the switching period devoted %to actual transitions, estimated as [2* (switch transi- tion time * 100 MHz)], assuming a 4x tapered buffer.
However, it can be observed that the maximum allowable DC voltages are also decreased, and in fact previously reported input voltage for single-switching-transistor converters is shown as a function of the technology used in FIG. 9. It is apparent that for CMOS devices with critical dimensions of 180 nm and below, the input voltage will fall below commonly-encountered supply voltages, such as 3.0, 3.6, and 5 volts, of importance in portable device applications. Under these conditions, a conventional buck converter circuit as depicted in FIG. 2 cannot operate reliably.
Therefore, there exists a need for a DC-DC converter that is simultaneously compact (including optimally fabrication of all active and passive components on a single semiconductor die), low in cost, and highly efficient even at small ratios of output to supply voltage and low output current.
It is desirable to have a method of reducing an output inductance of a DC-to-DC power converter while maintaining high-efficiency.